Principal Package Design engineer 

JOB Responsibilities: 
- Advanced package technology node engagement (Cowos/3D) 
- Bump pattern definition, pinout, package substrate stack-up and routing strategy definition 
- Perform package modeling 
- Guide package design or ATE design & yield of 16nm FinFET or below (16/14/10/7nm) for high-speed interface such as SERDES which at least 25Gbps and DDR3/4 
- Develop scripts for pre- and post-processing automation 

Masters in Electrical or Computer Engineering and at least 3 years of experience in the following areas (at least 3 items): 
-        Digital package design focused primarily on signal/power integrity 
-        DDR3/4 and LPDDR3/4 package design and analysis 
-        High-speed serial I/O (at least 25Gbps) package design and analysis 
-        One or more commercial SI tools such as Ansys tools, PowerSI and/or Sentinel-PSI 
-        Electromagnetic theory and its application to high-speed transmission lines 
-        Sigrity, Agilent, and MATLAB tools desirable 
-        Ansys HFSS or a similar 3D electromagnetic field solver 
-        Skill and experience of ATE & Yield is needed 
-      Bilingual in English and Chinese is required