Position Summary

The Front-End Design Engineer at Samsung Semiconductor Austin R&D Center (SARC) will be responsible for implementation of blocks for a high perf/low power CPU. To do this the designer will be using a combination of tools and hand design techniques. In this role the designer needs to interact with the RTL team and provide timing/power/area feedback during the RTL development phase of the project and later transition to design closure activities

Common Essential Duties & Resp.

RTL-to-netlist generation through synthesis

Formal verification of the netlist

Optimize blocks using Structured Datapath design style (handmap gates & placement)

Floorplaning/place & route of the block

perform timing analysis & optimize paths to meet timing/power/area targets

Background / Experience

Required

BSEE with 0-5 years relevant experience

Hands-on experience with the following is a plus:

Synopsys DC/Primetime/ICC

formal equivalence tools (Formality, Conformal)

Perl, TCL, Shell, and other script languages